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EDI88130CS
HI-RELIABILITY PRODUCT
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
s Access Times of 15*, 17, 20, 25, 35, 45, 55ns s Battery Back-up Operation * 2V Data Retention (EDI88130LPS) s CS1, CS2 & OE Functions for Bus Control s Inputs and Outputs Directly TTL Compatible s Organized as 128Kx8 s Commercial, Industrial and Military Temperature Ranges s Thru-hole and Surface Mount Packages JEDEC Pinout * * * * * * 32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102) 32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9) 32 lead Ceramic SOJ (Package 140) 32 pad Ceramic Quad LCC (Package 12) 32 pad Ceramic LCC (Package 141) 32 lead Ceramic Flatpack (Package 142) The EDI88130CS is a high speed, high performance, 128Kx8 bits monolithic Static RAM. An additional chip enable line provides system memory security during power down in non-battery backed up systems and memory banking in high speed battery backed systems where large multiple pages of memory are required. The EDI88130CS has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. A low power version, EDI88130LPS, offers a 2V data retention function for battery back-up applications. Military product is available compliant to MIL-PRF-38535.
*15ns access time is advanced information, contact factory for availability.
s Single +5V (10%) Supply Operation
FIG. 1
PIN CONFIGURATION
32 DIP 32 SOJ 32 CLCC 32 FLATPACK 32 QUAD LCC
PIN DESCRIPTION
I/O0-7 A0-16 WE CS1, CS2
29 28 27 26 25 24 23 22 21
TOP VIEW
A12 A14 A16 NC VCC A15 CS2
Data Inputs/Outputs Address Inputs Write Enable Chip Selects Output Enable Power (+5V 10%) Ground Not Connected
TOP VIEW
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AO I/OO I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 VCC 31 A15 30 CS2 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS1 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3
4
3
2
1
32
31
30
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20
WE A13 A8 A9 A11 OE A10 CS1 I/O7
OE VCC VSS NC
BLOCK DIAGRAM
Memory Array
I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6
AO-16
Address Buffer
Address Decoder
I/O Circuits
I/OO-7
WE CS1 CS2 OE
July 2001 Rev. 10
1
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EDI88130CS
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Industrial Military Storage Temperature, Ceramic Power Dissipation Output Current Junction Temperature, TJ -0.2 to 7.0 -40 to +85 -55 to +125 -65 to +150 1.7 40 175 Unit V C C C W mA C OE X X H L X CS1 H X L L L CS2 X L H H H X X H H L
TRUTH TABLE
WE Mode Standby Standby Output Deselect Read Write Output High Z High Z High Z Data Out Data In Power Icc2, Icc3 Icc2, Icc3 Icc1 Icc1 Icc1
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C)
Max Parameter Address Lines Data Lines Symbol CI CO Condition VIN = Vcc or Vss, f = 1.0MHz VOUT = Vcc or Vss, f = 1.0MHz LCC 6 8
CSOJ,DIP, Unit Flatpack
12 14
pF pF
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5 Typ 5.0 0 -- -- Max 5.5 0 Vcc +0.5 +0.8 Unit V V V V
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS (VCC = 5V, TA = -55C to +125C)
Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Symbol ILI ILO ICC1 VIN = 0V to VCC VI/O = 0V to VCC WE, CS1 = VIL, II/O = 0mA, CS2 = VIH CS1 VIH and/or CS2 VIL, VIN VIH or VIL CS1 VCC -0.2V and/or CS2 0.2V VIN Vcc -0.2V or VIN 0.2V IOL = 8.0mA IOH = -4.0mA (15-17ns) (20ns) (25-55ns) (17-55ns) (15ns) CS (17-55ns) CS (15ns) LPS Conditions Min -- -- -- -- -- -- -- -- -- -- -- 2.4 Typ -- -- Max 5 10 300 225 200 25 60 10 15 5 0.4 -- Units A A mA mA mA mA mA mA mA mA V V
Standby (TTL) Power Supply Current
ICC2
Full Standby Power Supply Current Output Low Voltage Output High Voltage
ICC3 VOL VOH
3 -- -- -- --
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480
480
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load
VSS to 3.0V 3ns 1.5V Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
Q 255 30pF Q 255 5pF
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2
EDI88130CS
AC CHARACTERISTICS - READ CYCLE (15 to 20ns) (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in Low Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Chip Enable to Power Up (1) Chip Enable to Power Down (1) Symbol JEDEC Alt. tAVAV tAVQV tE1LQV tE2HQV tE1LQX tE2HQX tE1HQZ tE2LQZ tAVQX tGLQV tGLQX tGHQZ tE1LICCH tE2HICCH tE1HICCL tE2LICCL tRC tAA tACS tACS tCLZ tCLZ tCHZ tCHZ tOH tOE tOLZ tOHZ tPU tPU tPD tPD 0 0 15 15 0 5 0 0 17 17 3 6 0 6 0 0 20 20 5 5 6 6 3 6 0 8 15ns* Min 15 15 15 15 5 5 7 7 3 7 Max Min 17 17 17 17 5 5 8 8 17ns Max Min 20 20 20 20 20ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. This parameter is guaranteed by design but not tested. * 15ns access time is advanced information, contact factory for availability.
AC CHARACTERISTICS - READ CYCLE (25 to 55ns) (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in Low Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Chip Enable to Power Up (1) Chip Enable to Power Down (1) Symbol JEDEC Alt. tAVAV tAVQV tE1LQV tE2HQV tE1LQX tE2HQX tE1HQZ tE2LQZ tAVQX tGLQV tGLQX tGHQZ tE1LICCH tE2HICCH tE1HICCL tE2LICCL tRC tAA tACS tACS tCLZ tCLZ tCHZ tCHZ tOH tOE tOLZ tOHZ tPU tPU tPD tPD 0 0 25 25 0 10 0 0 35 35 0 10 0 15 0 0 45 45 5 5 10 10 0 15 0 20 0 0 55 55 25ns Min 25 25 25 25 5 5 15 15 0 20 0 20 Max Min 35 35 35 35 5 5 20 20 0 25 35ns Max Min 45 45 45 45 5 5 20 20 45ns Max Min 55 55 55 55 55ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. This parameter is guaranteed by design but not tested.
3
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EDI88130CS
AC CHARACTERISTICS - WRITE CYCLE (15 to 20ns) (VCC = 5.0V, VSS = 0V, TA = 0C to +70C)
Parameter Write Cycle Time Chip Enable to End of Write Symbol JEDEC tAVAV tE1LWH tE1LE1H tE2HWH tE2HE2L tAVWL tAVE1L tAVE2H tAVWH tWLWH tWLE1H tWLE2L tWHAX tE1HAX tE2LAX tWHDX tE1HDX tE2LDX tWLQZ tDVWH tDVE1H tDVE2L tWHQX 15ns* Alt. tWC tCW tCW tCW tCW tAS tAS tAS tAW tWP tWP tWP tWR tWR tWR tDH tDH tDH tWHZ tDW tDW tDW tWLZ Min 15 12 12 12 12 0 0 0 12 12 12 12 0 0 0 0 0 0 0 7 7 7 3 Max Min 17 13 13 13 13 0 0 0 13 13 13 13 0 0 0 0 0 0 0 8 8 8 3 17ns Max Min 20 15 15 15 15 0 0 0 15 15 15 15 0 0 0 0 0 0 0 10 10 10 3 20ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Address Setup Time
Address Valid to End of Write Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1) Data to Write Time
7
8
8
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS - WRITE CYCLE (25 to 55ns) (VCC = 5.0V, VSS = 0V, TA = 0C to +70C)
Parameter Write Cycle Time Chip Enable to End of Write Symbol JEDEC Alt. tAVAV tWC tE1LWH tCW tE1LE1H tCW tE2HWH tCW tE2HE2L tCW tAVWL tAS tAVE1L tAS tAVE2H tAS tAVWH tAW tAVEH tAW tWLWH tWP tWLE1H tWP tWLE2L tWP tWHAX tWR tE1HAX tWR tE2LAX tWR tWHDX tDH tE1HDX tDH tE2LDX tDH tWLQZ tWHZ tDVWH tDW tDVE1H tDW tDVE2L tDW tWHQX tWLZ 25ns Min 25 20 16 16 0 0 0 20 20 20 20 20 0 0 0 0 0 0 0 15 15 15 3 0 0 0 25 25 30 30 30 0 0 0 0 0 0 0 20 20 20 3 Max Min 35 25 20 20 0 0 0 35 35 30 30 30 5 5 5 0 0 0 0 20 20 20 3 35ns Max Min 45 35 25 25 0 0 0 45 45 35 35 35 5 5 5 0 0 0 0 25 25 25 3 45ns Max Min 55 45 40 40 55ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
16
20
25
40
Address Setup Time
Address Valid to End of Write Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1) Data to Write Time
10
13
15
20
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
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4
EDI88130CS
FIG. 2
TIMING WAVEFORM - READ CYCLES
ADDRESS
tAVAV tAVQV
CS1
tE1LQV tE1LQX tE1LICCH
tE1HQZ tE1HICCL tE2LICCL
tAVAV
ADDRESS
ADDRESS 1 ADDRESS 2
Icc
tE2HQV
CS2
tE2HICCH tE2HQX
tAVQV
DATA I/O
tAVQX
DATA 1 DATA 2
OE
tGLQV tGLQX
DATA I/O
tGHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (CS1 AND/OR CS2 CONTROLLED, WE HIGH)
FIG. 3
WRITE CYCLE 1
ADDRESS
tAVAV tAVWH tWLWH
tAVWL
WE
tWHAX
tE1LWH
CS1
CS2
tE2HWH
tDVWH
tWHDX
DATA IN
tWLQZ
DATA OUT
tWHQX
WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED
FIG. 4
ADDRESS
WRITE CYCLES 2
tAVAV
WRITE CYCLES 3
tAVAV
ADDRESS
tAVE1L
WE
tE1LE1H
tE1HAX
WS32K32-XHXt t
AVE2H
E2HE2L
tE2LAX
WE
CS1
CS1
CS2
CS2
tDVE1H
DATA I/O
tE1HDX
DATA I/O
tDVE2L
tE2LDX
WRITE CYCLE 2 - EARLY WRITE, CS1 CONTROLLED
WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED
5
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EDI88130CS
DATA RETENTION CHARACTERISTICS (EDI88130LPS ONLY) (TA = -55C to +125C)
Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time (1) Operation Recovery Time (1) Sym VDD ICCDR TCDR TR Conditions VDD = 2.0V CS1 VDD -0.2V and/or CS2 VSS +0.2V VIN VDD -0.2V or VIN 0.2V Min 2 - 0 TAVAV* Typ - 0.5 - - Max - 2 - - Units V mA ns ns
NOTE: 1. Parameter guaranteed by design, but not tested. * Read Cycle Time
FIG. 5
DATA RETENTION - CS1 CONTROLLED
Data Retention Mode
Vcc
4.5V VDD
WS32K32-XHX
4.5V
tCDR
CS2
CS2 0.2V
tR
DATA RETENTION, CS2 CONTROLLED
FIG. 6
DATA RETENTION - CS2 CONTROLLED
Data Retention Mode
Vcc
4.5V VDD
WS32K32-XHX
4.5V
tCDR
CS2
CS2 0.2V
tR
DATA RETENTION, CS2 CONTROLLED
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6
EDI88130CS
PACKAGE 12:
32 PIN CERAMIC QUAD LCC
0.120 0.060 0.028 0.022 0.020 X 45 REF. 0.050 BSC. 0.560 0.540
0.458 0.442
0.055 0.045
0.040 X 45 REF.
ALL DIMENSIONS ARE IN INCHES
PACKAGE 9:
32 PIN SIDEBRAZED CERAMIC DIP (600 mils wide)
1.616 1.584
Pin 1 Indicator 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500
0.060 0.040
0.620 0.600
0.100 TYP
0.155 0.115
0.600 NOM
ALL DIMENSIONS ARE IN INCHES
PACKAGE 102:
32 PIN SIDEBRAZED CERAMIC DIP (400 mils wide)
1.616 1.584
Pin 1 Indicator 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500
0.060 0.040
0.420 0.400
0.100 TYP
0.155 0.115
0.400 NOM
ALL DIMENSIONS ARE IN INCHES 7
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EDI88130CS
PACKAGE 140:
32 LEAD CERAMIC SOJ
0.010 0.006 0.019 0.015
0.840 0.820
0.444 0.430
0.379 0.155 0.106
0.050 TYP
ALL DIMENSIONS ARE IN INCHES
PACKAGE 141:
32 PAD CERAMIC LCC
0.096 0.080 0.028 0.022 0.840 0.820
0.405 0.395
0.050 TYP
ALL DIMENSIONS ARE IN INCHES
PACKAGE 142:
32 PIN CERAMIC FLATPACK
0.830 0.810 0.007 0.003 0.370 0.250 1.00 REF 0.420 0.400 0.290 0.270 0.040 0.030 0.019 0.015 0.116 0.100
Pin 1
0.045 0.020
0.050 TYP
ALL DIMENSIONS ARE IN INCHES
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8
EDI88130CS
ORDERING INFORMATION EDI 8 8 130 CS X X X
WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 128Kx8 (130 = Dual CS) TECHNOLOGY: CS = CMOS Standard Power (5V) LPS = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) F = 32 lead Ceramic Flatpack (Package 142) L = 32 pad Ceramic LCC (Package 141) L32 = 32 pad Ceramic Quad LCC (Package 12) N = 32 lead Ceramic SOJ (Package 140) T = 32 lead Sidebrazed DIP, 400 mil (Package 102) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55C to +125C I = Industrial -40C to +85C C = Commercial 0C to +70C
9
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